Ștefan Ghețu

A cycle-accurate simulator and performance suite for RISC-V programs. The work I'm proudest of so far.

• 5-stage pipeline (IF/ID/EX/MEM/WB) with full data forwarding and RAW / load-use hazard detection
• Perceptron branch predictor (Jiménez & Lin) at 89.8% accuracy ~9% fewer cycles vs. always-stall
• Two-pass RV32I assembler, configurable LRU/LFU cache, FastAPI backend with a /compare endpoint benchmarking 30 configs in parallel
• Rewriting the core in Rust for faster experiments

An RTOS-inspired tick-based scheduler simulator built around a multi-class task hierarchy.

• Implemented and observing performance in regards to Cache Related Preemption Delay
• Multiple policies (Rate Monotonic, EDF, Deadline Monotonic) and task types (periodic, aperiodic, and sporadic ) behind a common Scheduler interface
• UUniFast task-set generation, soft real-time job dropping, CSV trace pipeline for offline analysis
• In progress: multi-core model with per-core ready queues and cache-aware migration penalties

A ptrace-based userspace debugger for x86-64 ELF binaries — the primitives GDB is built on, from scratch.

• INT3 breakpoints via masked PEEKDATA/POKEDATA read-modify-write, single-stepping, GPR snapshots
• Solved the canonical INT3 resume: on SIGTRAP, rewind RIP, restore the byte, single-step, reinject 0xCC
• Separate spawn vs. attach lifecycles; ELF symbol resolution for name-based breakpoints, disassembly via libcapstone
• RAII over kernel handles, Command + Observer + Factory patterns, verified by Catch2 tests